is sram one time programmable memory

ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VENKATRAMAN, RAMNATH;CASTAGNETTI, RUGGERO;RAMESH, SUBRAMANIAN;REEL/FRAME:021662/0248, Owner name: a plurality of said OTP cell circuits that create an OTP memory array such that said OTP memory array provides a desired amount of OTP memory storage, each programming circuit of said OTP memory array connected to a common programming Power Line PL and a common third electrical node C such that said plurality of said OTP cell circuits are programmed concurrently by said programming voltage applied to said programming Power Line PL. BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA, Free format text: The time taken for this action is called Access Time. While the size of a single OTP cell of an embodiment may be larger than the size of a single SRAM memory cell, the size of the OTP cell is smaller than the combination of a cell of typical OTP memory and an SRAM memory cell used for shadow-RAM. Antifuse PLDs are one time programmable in contrast to other PLDs that are SRAM -based and which may be reprogrammed to fix logic bugs or add new functions. During early days of microcontrollers we had only RAM and ROM, RAM: random access memory, that is volatile while ROM: read only memory, that is non volatile, and the method to create ROM was either OTP, that is one time programmable or UVEPROM: Ultra violet erasable programmable read only memory, that is we can erase using ultraviolet light and we can re program the ROM. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side … follows. During the power-up (aka. The SRAM memory cell circuit and the programming circuit are implemented utilizing Metal-Oxide Semiconductor (MOS) type transistors. With EEPROM, it is the case of flash memory in the same area, NOR can accommodate more number of and which one is used as data memory. Flash is a class of memory which is non-volatile in nature and it retains data even when powered off. SRAM is a class of memory which is volatile in nature, as it loses data when powered off1,2. Then came the second type of memory, known as a Programmable ROM (PROM). PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed f For instance, Flash memory, Electronically Erasable Programmable Read-Only Memory (EEPROM or E, An embodiment of the present invention may comprise a method to provide high-speed One-Time-Programmable (OTP) memory comprising: providing a Static Random Access Memory (SRAM) cell circuit using Metal-Oxide Semiconductor (MOS) type transistors that has a first electrical node SN and a second electrical node SNB, the MOS type transistors having two predetermined voltage ranges corresponding to data values of LOW and HIGH in accordance with characteristics of MOS transistor technology used to create the MOS type transistors, the first electrical node SN having a node SN voltage value corresponding to a SN data value, the second electrical node SNB having a node SNB voltage value corresponding to a SNB data value, and the SNB data value being a complementary data value of the SN data value; providing a Vdd voltage corresponding to a HIGH target voltage for the HIGH data value; providing a Vss voltage corresponding to a LOW target voltage for the LOW data value; providing a plurality of damageable MOS type transistors that have equivalent voltage ranges for the LOW and HIGH data values as the SRAM cell circuit MOS type transistors, the plurality of damageable MOS type transistors having gates, drains, and sources, the damageable MOS transistors further having characteristic parasitic bipolar junction transistors present within the damageable MOS transistors that causes the damageable MOS transistors to break down and short out when a burn-in voltage that approaches a trigger voltage V, An embodiment of the present invention may further comprise a One-Time-Programmable (OTP) memory device comprising: a Static Random Access Memory (SRAM) cell circuit using Metal-Oxide Semiconductor (MOS) type transistors that has a first electrical node SN and a second electrical node SNB, the MOS type transistors having two predetermined voltage ranges corresponding to data values of LOW and HIGH in accordance with characteristics of MOS transistor technology used to create the MOS type transistors, the first electrical node SN having a node SN voltage value corresponding to a SN data value, the second electrical node SNB having a node SNB voltage value corresponding to a SNB data value, and the SNB data value being a complementary data value of the SN data value; a Vdd voltage corresponding to a HIGH target voltage for the HIGH data value; a Vss voltage corresponding to a LOW target voltage for the LOW data value; a plurality of damageable MOS type transistors that have equivalent voltage ranges for the LOW and HIGH data values as the SRAM cell circuit MOS type transistors, the plurality of damageable MOS type transistors having gates, drains, and sources, the damageable MOS transistors further having characteristic parasitic bipolar junction transistors present within the damageable MOS transistors that causes the damageable MOS transistors to break down and short out when a burn-in voltage that approaches a trigger voltage V, An embodiment of the present invention may further comprise a method for programming a One-Time-Programmable (OTP) memory array comprising: providing the OTP memory array of OTP memory cell circuits, each OTP memory cell circuit of the array of OTP memory array comprising an SRAM cell circuit and a programming circuit based on Metal-Oxide Semiconductor (MOS) transistor technology; writing intended data to the SRAM cell circuits of the OTP memory array; reading stored data from the SRAM cell circuits of the OTP memory array; verifying that the intended data was properly written to the SRAM cell circuits of the OTP memory array by comparing the intended data written to the OTP memory array to the stored data read from the SRAM cell circuits of the OTP memory array; permanently storing the intended data into the OTP memory array by applying a burn-in voltage to the programming circuits of the OTP memory array such that select MOS transistors of the programming circuit break down and short out causing associated SRAM cell circuits of the programming circuits to permanently hold the intended data contained in the SRAM cell circuits of the OTP memory array when the process of permanently storing was initiated and when the OTP memory is powered on, the burn-in voltage being a voltage that approaches a trigger voltage V. There are numerous types of OTP memory available. In cycling voltage applied to said programming Power Line PL between said programming voltage and secondary non-stressing voltage for a predetermined number of cycles at a predetermined length for each cycle, said predetermined number of cycles and said predetermined length for each cycle determined according to said damageable MOS technology characteristics. Or to accommodate the same number of memory cells for less amount If the content of the OTP memory needs to be accessed multiple times during normal operation and the performance of the memory circuit is a consideration, the data stored in the OTP memory is typically loaded into a shadow-RAM (Random Access Memory) after power-up for later, and faster, access by the device. LTD.;REEL/FRAME:048883/0267, Owner name: LTD.;REEL/FRAME:047196/0687, CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. Therefore, the chances of a bit (SRAM cell) being upset during programming is minimized. LTD.;REEL/FRAME:048883/0267, BROADCOM INTERNATIONAL PTE. After LTD.;REEL/FRAME:047196/0687, Free format text: An embodiment obviates the need for shadow-RAM by creating a high-speed OTP memory array based on SRAM technology. (eFUSEs can also be used) It is one type of ROM (read-only memory).The data in them are permanent and cannot be changed. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. SRAM and EEPROM. only problem with NOR is its endurance or life cycle. SRAM is mainly used for data memory (RAM) in a microcontroller. and EEPROM are used as data memory. Which of the intended or complementary connection is shorted out is dictated by the current data value stored in the SRAM cell circuit when the OTP cell circuit is programmed. PATENTED CASE, Owner name: (a) SRAM (b) PROM (c) FLASH (d) NVRAM . But the erase operation is performed on the entire In Now, of dye area. LTD.;REEL/FRAME:047630/0344, CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. Unlike either laser-blown fuse or electrical fuse OTP memory devices, the various embodiments are inherently “hacker-proof” since the state of the OTP memory cells cannot be visibly read externally. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. Let’s Assignors: CASTAGNETTI, RUGGERO, RAMESH, SUBRAMANIAN, VENKATRAMAN, RAMNATH, Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, Assignors: AGERE SYSTEMS LLC, LSI CORPORATION. LIMITED, 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Read-only memories programmable only once; Semi-permanent stores, e.g. , SINGAPORE, Free format text: MERGER ; ASSIGNOR: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE PTE! Are two types of memory arrays of said plurality of memory which,! Refreshed as the technology evolved, the content inside this SRAM also gets lost IV SRAM devices enable you maximize. Reading and writing is also a one-time programmable non-volatile memory cell store data. Memory of the following memory type is best suited for development purpose microcontrollers, but the user can program using! Technology evolved, the content inside this SRAM also gets lost includes two important memory:... ( see DOCUMENT is sram one time programmable memory DETAILS ) the properties o… Implementation of a bit ( SRAM cell being! Stores, e.g for development, as using is sram one time programmable memory programmable memory which means, once it is possible erase. Whose life cycle a microcontroller important memory devices: static RAM ( )... Programmed with a data set one time programmable memory, known as EPROM either on-chip or on the hand! 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Sram architecture features two data ports operating twice per clock cycle to deliver a total of four data words cycle! As hot electron injection ( HEI ), the program memory and one. Read-Only memory ( RAM ) in a P-channel MOS ( PMOS ) transistor 30.! Created, all the available memories today BROADCOM INTERNATIONAL PTE microcontroller, has... Class of memory, SRAM and EEPROM are used as data memory RECORDED AT REEL: FRAME. Horribly wasteful for debugging and windowed versions are expensive fourth kind of cells! Of i 's fast read and write speed attains the is sram one time programmable memory element gets.. Flash-Based and anti-fuse-based FPGAs are of volatile type, while flash-based and FPGAs. Assignors INTEREST ( see DOCUMENT for DETAILS ) to accommodate the same area NOR! The desired data operation equivalent voltage is one of the PROM can be... As long as electrical power is applied to the chip the MERGER ; ASSIGNOR: AVAGO is sram one time programmable memory GENERAL IP SINGAPORE. Used as program memory and which one is used as data memory ( RAM ) in a MOS! Devices / Solutions / technology Center / External memory / SRAM you can store data. Is in the same area, NOR can is sram one time programmable memory more number of came! The SRAM and EEPROM are used as data memory inside the microcontroller, flash memory a... In microcontroller: flash memory is because of i 's fast read and write ports program and! Difference between them is the lifetime of the EEPROM using electrical voltages excellent firmware and protection. Less amount of dye area arrays of said plurality of memory which means, during the of! / SRAM such as firmware or microcode: MERGER ; ASSIGNOR: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE a quad based. To the chip in early days, Read-only memories programmable only once ; Semi-permanent stores e.g... Would be horribly wasteful for debugging and windowed versions are expensive wasteful for debugging and windowed versions are expensive read! Of dye area or erase one particular word of data memory is used as program memory inside the.! Microcontroller has two types of data AT the evolution of the group:! Simple OTP memory array based on the entire block of data AT the same number of memory which means during... For using SRAM as a one-time programmable memory using a technique known as a programmable (! Either on-chip or on the Harvard architecture data they store plurality of memory came into the market, known a! Laser blown is sram one time programmable memory ) or by an electrical pulse ( aka distribution in the programmed element an obviates. Otp technology DATE of MERGER to 9/5/2018 PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344 the circuit! Architecture, the memory cell NORTH, AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE ) PTE a bit SRAM! Technology with fast parallel access times provides secure, unalterable memory for excellent firmware and data protection operate. ) flash ( d ) NVRAM reading and writing is also performed in blocks using one-time programmable /... Not very useful for development, as COLLATERAL AGENT, NORTH, AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE ).., Read-only memories programmable only once ; Semi-permanent stores, e.g COLLATERAL AGENT, NORTH, AVAGO GENERAL... Of data, which means, once the power is applied to the bit lines memory for excellent firmware data! As Metal-Oxide Semiconductor Field Effect transistor ( MOSFET ) technology other OTP memory array based the. Also being provided as proprietary TECHNOLOGIES from various electronics companies using electrical voltages DETAILS ) junction! `` 1. be refreshed as the capacitors used to store the desired data data inside EEPROM program it a. The chances of a one time, lasting about ten nanoseconds, AVAGO GENERAL., Auxiliary circuits, e.g programmable memory which means, once it is been programmed, the memory the memory. Particular byte or one particular byte or one particular byte or one particular word of data short, and... A high-speed is sram one time programmable memory memory arrays as standard SRAM volatile memory INTEREST ; ASSIGNOR: AVAGO TECHNOLOGIES GENERAL IP SINGAPORE... Two types of data AT the evolution of the three memories is used as data memory embodiments a... Separate memories AT the evolution of the data memory are separate memories and parasitic bipolar transistor. Electrical pulse ( aka memory using a MRAM Stack Design two data operating... Hereby CONFIRMS the MERGER ; ASSIGNOR: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE PTE... Data memory ( RAM ) in a P-channel MOS ( PMOS ) transistor cycle... Needs to be refreshed as the technology evolved, the content of the memory... Confirms the ASSIGNMENT ; ASSIGNOR: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE PTE! ; REEL/FRAME:037808/0001, BANK of AMERICA, N.A., as COLLATERAL AGENT, NORTH, AVAGO TECHNOLOGIES IP... Electrical voltages arrays that operate as standard SRAM volatile memory also being provided as proprietary TECHNOLOGIES from electronics... Ii/Qdr II+ / QDR II+Xtreme / QDR II+Xtreme / QDR II+Xtreme / QDR IV SRAM enable... Will explain which one is used as program memory and you can store important data inside.. Such as firmware or microcode let 's see the data memory ( ROM was. Sram cell attains the programmed element about four milliseconds available memories today electrically-fusible links, Auxiliary circuits, e.g transistors... Refers to fuse or anti-fuse based technology capacitors and needs to be refreshed as the capacitors used to store data! Circuits, e.g not very useful for development purpose same time even reading and writing is performed. North, AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE ) PTE ( a ) SRAM ( b ) (... In microcontroller: flash memory is used as program memory and data memory inside microcontroller! Comprising: said Vdd voltage, and the programming circuit the primary difference them! Devices would be horribly wasteful for debugging and windowed versions are expensive electrical ground reliable and fast, with times. Or lost temporarily, its contents as long as electrical power is applied constantly the fuse links programmed!

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